(1) Field of the Invention
This invention relates to a semiconductor memory and a method for testing a semiconductor memory and, more particularly, to a semiconductor memory an operation mode of which can be set from the outside and a method for testing such a semiconductor memory.
(2) Description of the Related Art
In recent years pseudostatic random access memories (SRAM) in which memory cores for large-capacity low-cost dynamic random access memories (DRAM) are used and in which refresh operation can be performed inside memory elements have been used especially in portable telephones and the like.
Such a pseudostatic RAM includes a plurality of configuration registers (CR) which hold internal operation mode information by a command sent from the outside of a chip.
FIG. 10 is a view showing an example of a conventional CR setting sequence.
As shown in FIG. 10, to perform CR setting, a specific address A for register access in a memory determined by specifications is accessed in the order of steps 1 through 6. In the step 1, data RDa is read out first from the address A (RD). In the steps 2 and 3, the data RDa read out is then written to the address A in succession (WR). When memory access is performed in the order of the steps 1 through 3, the determination that a command to request entry to a CR access mode is issued is made. In and after the step 4 in which entry to the CR access mode has been made, writing data to a memory cell and reading out data from a memory cell are stopped. In the step 4, “CR set” or “CR verify” is selected by data inputted to, for example, a pad DQ0 of a plurality of data pads (used both for inputting data and for outputting data) of the semiconductor memory.
The “CR set” is the operation of writing operation mode information to a CR (updating operation mode information written to a CR). The “CR verify” is the operation of outputting operation mode information written to a CR. If the “CR set” is selected in the step 4, a plurality of CRs are set according to 8-bit data sent from the pad DQ0 and pad DQ1 through DQ7 on a time division basis at the time of performing writing operation in the steps 5 and 6. An address used at the time of performing the writing operation is also the specific address A for register access. In some cases, pieces of operation mode information set in the steps 4 through 6 are referred to as CR-Key0, CR-Key1, and CR-Key2 respectively.
By the way, the technique of a data pad compression test mode by which more chips are measured simultaneously by limited terminals (hereinafter referred to as tester pins) of a test circuit (not shown) is known as a technique for reducing the cost of testing semiconductor memories. With this technique, test data inputted to part of data pads assigned to tester pins is used for representing test data to be inputted to the other data pads not assigned to tester pins. That is to say, a plurality of data pads are compressed. By doing so, the number of tester pins assigned to data pads of one chip is reduced.
FIG. 11 is a view showing an example of data pad compression. It is assumed that out of 32 pads DQ0 through DQ31, the pads DQ0, DQ5, DQ8, and DQ13 are assigned to tester pins of a test circuit. Test data to be inputted to the other data pads is determined on the basis of test data inputted to the pads DQ0, DQ5, DQ8, and DQ13 in accordance with codes (hereinafter referred to as subcodes) inputted at the time of performing data pad compression. As shown in FIG. 11, the eight pads DQ0, DQ2, DQ4, DQ6, DQ16, DQ18, DQ20, and DQ22 can be compressed into the pad DQ0 by using subcodes a08, a09, and a10, which are part of address information, on the basis of the test data inputted to, for example, the pad DQ0. The subcodes are for designating whether the test data inputted to the pads DQ0, DQ5, DQ8, and DQ13 assigned to the tester pins should be inverted or be used in its original condition. For example, if the value of the subcode a08 is “1,” then a value obtained by inverting the value inputted to the pad DQ0 is used as data to be inputted to the pads DQ2 and DQ18 in the semiconductor memory.
Such data pad compression is performed by the following data pad compression circuit included in the semiconductor memory.
FIG. 12 is a view showing part of a data pad compression circuit.
FIG. 12 shows part of a data pad compression circuit 500 used for representing data to be inputted to the pads DQ2, DQ4, D126, DQ16, DQ18, DQ20, and DQ22 by the use of the data which is inputted to the pad DQ0 and which is shown in FIG. 11.
The data pad compression circuit 500 includes switching circuits 501, 502, 503, and 504 connected to the pads DQ0, DQ2, DQ4, and DQ6 respectively. In addition, the switching circuits 502, 503, and 504 are connected to the pads DQ0 to which a tester pin is connected.
Each of the switching circuits 501, 502, 503, and 504 includes an inverting circuit Inv and two switches Sw1 and Sw2. Each switch Sw1 is used for determining whether to invert the data from the pad DQ0 by the inverting circuit Inv or to use the data from the pad DQ0 in its original condition. This determination is made according to the above subcode a08, a09, or a10. The state of the switch Sw1 included in the switching circuit 501 is fixed regardless of the value of a subcode.
Each of the switches Sw2 included in the switching circuits 502, 503, and 504 is used for selecting data from the pad DQ2, DQ4, or DQ6 or the data from the pad DQ0 (or data obtained by inverting the data from the pad DQ0) selected by each switch Sw1. When data pad compression is not performed (normal operation or the like other than test operation is performed), the data from the pad DQ2, DQ4, or DQ6 is selected. When data pad compression is performed, the data from the pad DQ0 is selected. The state of the switch Sw2 included in the switching circuit 501 is fixed so as to always select the data from the pad DQ0.
The pads DQ16, DQ18, DQ20, and DQ22 are connected to delay circuits 511, 512, 513, and 514, respectively, which delay input data by time corresponding to delays that occur in the switching circuits 501, 502, 503, and 504 respectively.
In addition, the data pad compression circuit 500 includes word structure switching circuits 521, 522, 523, 524, 525, 526, 527, and 528 for switching word structure in the semiconductor memory between 32 bits and 16 bits. When data pad compression is performed, each of switches Sw3 included in the word structure switching circuits 521 through 528 functions so as not to select the data from the pad DQ16, DQ18, DQ20, or DQ22.
With conventional semiconductor memories, the number of tester pins assigned to data pads of one chip at test time can be reduced by using the above data pad compression circuit 500.
A semiconductor integrated circuit device which can perform an operation test at an actual operation frequency by using a low-cost test circuit that provides a low-frequency test clock is disclosed in, for example, Japanese Patent Laid-Open Publication No. 2001-319500.
With the conventional semiconductor memories, however, a plurality of CRs cannot be set to desired values at test time if data pad compression is used. This problem will now be described concretely.
FIG. 13 is a view showing the operation of a conventional semiconductor memory performed in the case of combining data pad compression and CR setting.
To enter a test mode, a test start signal which is an illegal command is generated by, for example, making an output enable signal /OE and a write enable signal /WE the low (L) level and making byte mask signals /BO, /Bl, _, and /Bn for controlling writing byte by byte the high (H) level. At this time the operation of writing all bit masks occurs, depending on specifications. If data pad compression is used, an address including an entry code for data pad compression and a subcode for designating CR data is inputted at the time of entering the test mode. In FIG. 13A, a CR setting sequence can progress to step 4. This is the same with FIG. 10. However, if the subcode is not variable, CR-Key1 and CR-Key2 to be inputted in steps 5 and 6 respectively may be equal to the CR-Key0 and an arbitrary change cannot be made.
Therefore, as shown in FIG. 13B, the method of entering the test mode again after the step 4 and inputting an address including a subcode for the CR-Key1 may be applied. In this case, however, the operation of writing all the bit masks occurs and writing operation is performed at addresses which do not match the specific address A for CR setting. This leads to exiting the CR setting sequence.